Computer Organisation and Architecture: An Introduction - download pdf or read online

By B.S. Chalk

This publication describes how a working laptop or computer works and explains how a few of the parts are prepared and interconnected to supply a platform upon which courses could be achieved. It takes an easy, step by step strategy compatible for first yr undergraduates coming to the topic for the 1st time. the second one version of this publication has been completely up-to-date to hide new advancements within the box and comprises new diagrams and end-of-chapter routines. it's going to even be followed by way of a lecturer and scholar site so one can comprise options to workouts, additional workouts, PowerPoint slides and the entire resource code utilized in the publication.

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Memory systems are described further in Chapter 6. 5 Summary Computer chips, however complicated, are made from combinations of a few simple logic gates. These gates may be arranged so that the output is only dependent on the current inputs. Such circuits are termed combinational logic circuits. If the output is dependent upon the current state of the outputs, as well as the inputs, then they are referred to as sequential logic circuits. 39 Computer organisation and architecture Although computer logic is based on only 2 states, the output buffers on many chips use a third state called a high-impedance state.

2. 3 Binary up-counter A counter is a circuit that passes through a sequence of well defined states on each transition of an input clock. g. 1100 Q Q2 D C Q Q1 D Q Q0 D C Q C Clock 000, 001, 010, 011, . . after each clock pulse. 3). The circuit uses three negative going edge triggered D-type flip-flops. The leftmost flip-flop or first stage of the counter is connected to the input clock, the other flip-flops being clocked from the output of their adjacent stages. The input to each flip-flop is derived from its Q output.

6 If R is taken high, then Q goes low forcing Q high. Q holds G1 low so that the outputs remain unchanged when R returns to 0. The circuit is now in its original state. 9 While the clock is high, the output will follow the D input. 10 The read line would need to be taken ‘high’, so that if the corresponding Q output was high, the AND gate would signal 1 and if the Q output was ‘low’, the AND gate would signal 0. 11 Each Q output will initially be 1. 40 Boolean logic EXERCISES 1 Complete the truth tables for the following circuit.

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