Advanced Parallel Processing Technologies: 8th International - download pdf or read online

By Liqiang He, Cha Narisu (auth.), Yong Dou, Ralf Gruber, Josef M. Joller (eds.)

This e-book constitutes the refereed lawsuits of the eighth foreign Workshop on complex Parallel Processing applied sciences, APPT 2009, held in Rapperswil, Switzerland, in August 2009.

The 36 revised complete papers awarded have been rigorously reviewed and chosen from seventy six submissions. All present points in parallel and dispensed computing are addressed starting from and software program matters to algorithmic elements and complicated functions. The papers are equipped in topical sections on structure, graphical processing unit, grid, grid scheduling, cellular software, parallel program, parallel libraries and performance.

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Extra info for Advanced Parallel Processing Technologies: 8th International Symposium, APPT 2009, Rapperswil, Switzerland, August 24-25, 2009 Proceedings

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Future CMP will integrate more cores on a chip to increase the performance, meanwhile will increase the on-chip cache size to reduce access latency. The increasing number of cores and growing cache capacity will challenge the design of on-chip cache hierarchy which is now working well on 2 or 4-core CMP. When CMP is scaled to tens or even hundreds of cores, the organization of on-chip cache and the design of cache coherence will become one of the key challenges. There have been dance-hall CMP architectures with processing cores on one side and shared L2 cache on the other side, which are connected by bus or network [25].

2. 2 for simplicity). The events triggering Fast Directory state transition have two sources: local router and L2 cache slice. Compared to baseline protocol, several types of messages are added for communication between two level directories. The added types of messages are summarized in Table 1. 3. Messages triggering L2 cache transitions are GETLINE and PUTLINE from Fast Directory. Upon receiving the PUTLINE, State and Dir field in L2 cache line are updated if a match is found. When cache line in L2 cache slice is replaced, the INVLINE, which comprises of State and Dir of the cache line, will be sent to Fast Directory.

In the worst cases, the number of directory vectors used in L2 cache is equal to the number of data blocks of L1 caches able to contain at any time when CMP is running. Since the capacity of L1 caches is far smaller than that of L2 cache, most of directory vectors are unused and wasted. In this paper, we firstly analyze the occupation of directory vectors in shared L2 cache of CMP. Experiment results show that the average number of blocks cached to L1 caches does not exceed 41% of the capacity of L1 caches due to redundant copies existing in L1 caches.

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